Technical Field
The present disclosure relates to a current converter with control of the current on the primary winding side and compensation of the propagation delay. In particular, the present disclosure regards a converter that may be used in a power supply aimed at the market of solid-state-lighting (SSL) apparatus, and more in particular to apparatus comprising lamps including arrays of light-emitting diodes (LEDs).
Description of the Related Art
Offline-driving power supplies of lighting apparatus that use LEDs comprise a control circuit and a transformer for maintaining a safety insulation between the control circuit and the load (LEDs). In these circuits, it is frequently desirable to regulate the d.c. output current used for driving the LEDs without making use of feedback circuits that use signals acquired on the secondary-winding side. In this way, on the secondary side of the transformer, there is no need of current-detection elements, reference-voltage sources or error amplifiers, nor possible optical couplers for transferring the error signal to the control circuit arranged on the primary side. Frequently, a high power factor (Hi-PF, higher than 0.9) is further desirable in order to meet the emission limits of current harmonics (according to the standards IEC 61000-3-2 in Europe and JEITA-MITI in Japan).
In order to obtain the above characteristics, switching converters of a Hi-PF flyback type are known, which are made, for example, according to the circuit scheme of FIG. 1 (see also C. Adragna “Primary-Controlled High-PF Flyback Converters Deliver Constant Dc Output Current” Europe Power Electronics Conference, September 2011, which are referred to for further details).
FIG. 1 shows a power supply 1 including a bridge rectifier 2 and a flyback converter 3.
The bridge rectifier 2 has two input terminals 10a, 10b, designed to receive an a.c. supply voltage Vac at a frequency fL, and two output terminals supplying an input voltage Vin(θ), where θ is the phase of the supply voltage Vac. The output terminals of the bridge rectifier 2 are connected to a first reference potential line (first ground 12) and to an input node 13, respectively.
The flyback converter 3 comprises a filtering capacitor Cin, connected between the input node 13 and the first ground 12 and operating as high-frequency smoothing filter; a transformer 4 including a primary winding Lp, a secondary winding Ls, and an auxiliary winding Laux; a control module 15; a resistive divider 16 including a first dividing resistor Ra and a second dividing resistor Rb; a power switch M, formed by a power transistor, for example a MOSFET; an auxiliary sensing resistor 21, having a resistance Raux; a primary sensing resistor 19 having a resistance Rs; and a clamping circuit 20.
In detail, the primary winding Lp of the transformer 4 has a first terminal 4a connected to the input node 13 and a second terminal 4b. The secondary winding Ls has a first terminal 4c and a second terminal 4d, the latter connected to a second reference potential line (second ground 17). The auxiliary winding Laux has a first terminal 4e connected to the first ground 12 and a second terminal 4f. The primary, secondary and auxiliary windings Lp, Ls, Laux are coupled together as illustrated in FIG. 1, with positive terminals 4b, 4c, and 4f. 
The first dividing resistor Ra is connected between the input node 13 and an intermediate node 14. The second resistor Rb has a first terminal connected to the intermediate node 14 and a second terminal connected to the first ground 12. The intermediate node 14 is coupled to a first input terminal MULT of the control module 15 and supplies a first voltage signal A(θ) proportional to the input voltage Vin(θ) through the dividing ratio Kp=Rb/(Ra+Rb) of the resistive divider 16, according to Eq. (1) below:A(θ)=KpVin,pk sin θ  (1)where Vin,pk=√{square root over (2)}Vin 
The auxiliary sensing resistor 21 is connected between the second terminal 4f of the auxiliary winding Laux and a second input terminal ZCD of the control module 15. The primary sensing resistor 19 is connected between the source terminal of the power switch M and the first ground 12. Further, the source terminal of the power switch M is connected to a third input terminal CS of the control module 15 and supplies thereto a sensing voltage Vcs(t,θ), directly proportional to the current in the primary winding Lp when the power transistor M is on, i.e., during magnetization of the primary winding Lp. In fact, the primary sensing resistor 19 detects the current Ip(t,θ) flowing in the primary winding Lp when the power switch M is on.
The transistor M further has its drain terminal connected to the second terminal 4b of the primary winding Lp and its gate terminal connected to an output terminal GD of the control module 15.
The clamping circuit 20 is arranged between the first and the second terminal 4a, 4b of the primary winding Lp for limiting voltage spikes on the drain terminal of the switch M, caused, for example, by parasitic inductances.
On the side of the secondary winding Ls, the flyback converter 3 comprises a output diode D and an output capacitor Cout. The output capacitor Cout is for example of an electrolytic type and has positive and negative plates coupled to a first output terminal 22 and to a second output terminal 23, which are in turn coupled to a load 18. The second output terminal 23 is coupled to the second ground 17. The output diode D has its anode connected to the first terminal 4c of the secondary winding Ls and has its cathode connected to the first load terminal 22. The voltage across the output capacitor Cout thus is an output voltage Vout supplied to the load 18, here a series of diodes, for example LEDs.
The control module 15 comprises a reference current source stage 24 and a comparator stage 25.
In particular, the reference current source stage 24 (described in detail in patent application US 2013/0088897) has a first input connected to the first input terminal MULT of the control module 15, a second input connected to a fourth terminal CT of the control module 15, and an output 27 generating a reference voltage VcsREF(θ) variable as a function of the phase θ of the supply voltage Vac, as explained in detail hereinafter.
The comparator stage 25 comprises a comparator 26, a latch flip-flop 28 of a set-reset type, a driver 30, a start-up circuit 32, a logic gate 34 of an OR type, and a zero-crossing detector (ZCD) 36.
The comparator 26 has an inverting input connected to the output 27 of the reference current source stage 24 and a non-inverting input connected to the third input terminal CS of the control module 15.
The output of the comparator 26 is connected to the reset input R of the flip-flop 28, the output Q whereof is connected to the input of the driver 30, coupled to the output terminal GD of the control module 15. The output Q of the flip-flop 28 is further connected to the set input of the flip-flop 28 through the start-up circuit 32. In detail, the input of the start-up circuit 32 is connected to the output Q of the flip-flop 28, and the output of the start-up circuit 32 is connected to a first input of the first logic gate 34. The first logic gate 34 has a second input connected to a first output of the ZCD circuit 36 and an output coupled to the set input of the flip-flop 28. The ZCD circuit 36 has an input connected to the second input terminal ZCD of the control module 15.
The reference current source stage 24 comprises a voltage-controlled current source 40 having a control terminal connected to the intermediate node 14; a voltage divider 41, connected between the intermediate node 14 and the fourth terminal CT of the control module 15; a first switch 42; a second switch 43; and a fourth resistor RT.
The current source 40 has an output terminal 44 supplying a current ICH(θ) proportional to the input voltage Vin(θ). The first switch 42 is connected between the output terminal 44 of the current source 40 and the first ground 12. The second switch 43 is connected between the output terminal 44 of the current source 40 and the fourth terminal CT of the control module 15. The fourth resistor RT is coupled between the fourth terminal CT of the control module 15 and the first ground 12 and generates a second voltage signal B(θ).
The switches 42, 43 are governed by phase signals FWN and FW of a logic type, equal and in phase opposition, generated by the ZCD circuit 36. The fourth terminal CT of the control module 15 is connected to an external capacitor CT of high value, chosen so that, at least to a first approximation, the a.c. component (at a frequency equal to twice the frequency of the supply voltage Vac) of the second voltage signal B(θ) is negligible as compared to the d.c. component B0. This condition is generally met also because in Hi-PF flyback converters the control loop has a bandwidth much lower than the frequency of the supply voltage Vac.
Operation of the power supply 1 of FIG. 1 is described hereinafter, with reference to FIGS. 2 and 3, and is described in detail in the paper by C. Adragna referred to above.
It should be noted that, in the flyback converter 3, when operating in Hi-PF condition, the filtering capacitor Cin does not operate as energy reservoir so that the input voltage Vin is a rectified sinusoid (Vin(θ)=Vin,pk|sin θ| with θϵ (0,π).
In these conditions, the voltage A(θ) is proportional to the input voltage Vin(θ) according to Eq. (1). Furthermore, since, as mentioned above, the second voltage signal B(θ) may be approximated with the respective d.c. value B0, the reference voltage VcsREF(θ) on the output of the voltage divider 41 is:
                                          V            csREF                    ⁡                      (            θ            )                          =                              K            D                    ⁢                                    A              ⁡                              (                θ                )                                                    B              o                                                          (        2        )            where KD is a proportionality constant, equal to the gain of the voltage divider 41. The reference voltage VcsREF(θ) is thus a rectified sinusoidal voltage, the value whereof depends upon the effective value of the supply voltage Vac on the basis of Eq. (1).
The reference voltage VcsREF(θ) is compared by the comparator 26 with the sensing voltage Vcs(t,θ), which is proportional to the current Ip(t,θ) in the primary winding Lp and in the switch M, when the latter is on.
Assuming that the switch M is initially closed, the current Ip(t,θ) through the primary winding Lp is initially increasing, as is the sensing voltage Vcs(t,θ). When the latter reaches the reference voltage VcsREF(θ), the comparator 26 switches and resets the output of the flip-flop 28. The power switch M is thus turned off. In this way, the first voltage signal A(θ), which as said has a rectified sinusoid shape, determines the peak value of the current Ip(t,θ) in the primary winding Lp, which is thus enveloped by a rectified sinusoid.
When the switch M turns off, the energy stored in the primary winding Lp is transferred by magnetic coupling to the secondary winding Ls and thus to the output capacitor Cout and to the load 18 until the secondary winding Ls is demagnetized completely.
After switching off of the switch M and as long as current flows in the secondary winding Ls, the voltage of the drain terminal of the switch M is equal to Vin(θ)+VR, where VR is the so-called reflected voltage, equal to n·Vout, where n is equal to the ratio between the number of the turns of the primary winding Lp and the number of the turns of the secondary winding Ls of the transformer 4.
After demagnetization of the secondary winding Ls, the diode D switches off and the drain terminal of the switch M becomes floating and tends to assume a voltage equal to the instantaneous value of the input voltage Vin(θ), through damped oscillations caused by a parasitic capacitance resonating with the primary winding Lp. However, the rapid voltage drop on the drain terminal of the switch M following demagnetization of the transformer 4 is coupled to the second input terminal ZCD of the control module 15 and thus to the ZCD circuit 36 through the auxiliary winding Laux and the third resistor Raux, as described in greater detail hereinafter.
The ZCD circuit 36 generates a pulse S on its output connected to the comparator 26 whenever it detects that a falling edge of the voltage on the second input terminal ZCD of the control module 15 drops below a threshold (VZCDt in FIG. 2). This pulse forces setting of the flip-flop 28, the output of which switches, turning on the power switch M and causing start of a new switching cycle.
The start-up circuit 32 enables, through the logic gate 34, starting of the first switching cycle after turning-on of the flyback converter 3, i.e., when no signal is yet present on the second input terminal ZCD of the control module 15, and further prevents the flyback converter 3 from remaining blocked if for some reason the signal on the second input terminal ZCD of the control module 15 is lost.
The ZCD circuit 36 also generates the phase signals FW and FWN, which are supplied to the switches 42, 43 (as illustrated in FIG. 2 for the signal FW). In detail, the phase signal FW is high during transformer demagnetization and is used for generating the correct value of the second voltage signal B(θ) so as to regulate the desired value of the d.c. output current, as demonstrated in the cited paper by C. Adragna.
In the circuit of FIG. 1, when the switch M is on, the second input terminal ZCD of the control module 15 is connected (by a controller—not illustrated) to the first ground 12. Thus, the voltage across the auxiliary sensing resistor 21 is equal to the auxiliary voltage Vaux on the auxiliary winding Laux. In this period, the voltage drop on the primary sensing resistor 19 and on the switch M is negligible, and the input voltage Vin is substantially entirely applied on the primary winding Lp, between the terminals 4a and 4b. Consequently, the auxiliary voltage Vaux and the current in the auxiliary sensing resistor 21 are proportional to the input voltage Vin.
When the switch M turns off, the second input terminal ZCD of the control module 15 is decoupled from the first ground 12, and the voltage VZCD on the second input terminal ZCD follows the plot of the output voltage Vout according to a proportionality coefficient linked to the turn ratio between the secondary winding Ls and the auxiliary winding Laux. After demagnetization of the secondary winding Ls, in particular, the voltage on the second input terminal ZCD tends to rapidly drop, as the current in the auxiliary sensing resistor 21, as illustrated in detail in FIG. 2.
Examples of the signals generated in the flyback converter 3 are represented in FIG. 2, where some quantities that follow the pattern of the input voltage Vin have rectilinear stretches, given that the switching frequency fs (of the order of kilohertz) is much higher than the frequency fL of the input voltage Vin (generally, 50-60 Hz).
In particular, FIG. 2 shows the following quantities:                the voltage VDS between the drain and source terminals of the switch M;        the voltage Vin,pk sin θ, where Vin,pk is the peak value of the input voltage Vin;        the voltage Vaux on the auxiliary winding Laux;        the voltage VZCD on the second input terminal ZCD of the control module 15;        the threshold VZCDt of the voltage VZCD where the ZCD circuit 36 generates a pulse supplied to the logic gate 34;        the set and reset pulses S, R supplied to the flip-flop 28;        the voltage VGD supplied on the output terminal GD of the control module 15 and driving turning-on and turning-off of the switch M;        the sensing voltage Vcs(t,θ);        the current Is(t,θ) in the secondary winding Ls; and        the freewheel phase signal FW, when demagnetization of the transformer 4 occurs.        
Furthermore, FIG. 2 highlights the following periods:                the period TON, when the switch M is on, thus representing the magnetization period of the core of the transformer 4;        the period TFW, when the core of the transformer 4 demagnetizes; and        the period TR, i.e., the period that elapses between complete demagnetization of the core of the transformer 4 and subsequent turning-on of the switch M, i.e., start of the new magnetization of the core of the transformer 4.        
The switching period T is thus given by T(θ)=TFW(θ)+TR+TON.
The resulting plots of the currents Ip(t,θ), Is(t,θ), as well as the corresponding envelopes of the corresponding peaks Ipkp(θ), Ipks(θ) and the cycle-by-cycle average Iin(θ) of the current in the primary winding Lp are represented in FIG. 3.
For practical purposes, the flyback converter 3 is of the quasi-resonant type. In fact, turning-on of the transistor M is synchronized with the instant of complete demagnetization of the transformer 4 (i.e., with the instant when the current in the secondary winding Ls goes to zero), albeit with a delay. Turning-off of the transistor M is instead theoretically determined by detecting when the current Ip in the primary winding Lp reaches the provided threshold (VcsREF(θ)/Rs). Furthermore, the flyback converter 3 is of the current-mode control type, and in particular of the peak-current-mode control type. Again, since the peak envelope of the current flowing in the sensing resistor Rs and thus in the primary winding Lp is sinusoidal, a power factor higher than 0.9 is obtained.
As shown in the paper by C. Adragna referred to above, the regulated d.c. output current Iout that flows in the load 18 is given by:
                              I          out                =                                            nK              D                                                                                  ⁢                              2                ⁢                                                                  ⁢                                  RsG                  M                                ⁢                                  R                  T                                                              .                                    (        3        )            where n is the turn ratio between the primary winding Lp and the secondary winding Ls of the transformer 4, KD is the gain of the divider 41 (see Eq. (2)) and GM is the transconductance of the current source 40. Consequently, with the instant control scheme that uses only quantities available on the primary winding Lp side of the transformer 4, the mean output current Iout depends ideally only upon external parameters, that may be selected by the user, such as n and Rs, or by fixed parameters such as GM, RT, and KD and does not depend upon the output voltage Vout or the input voltage Vin or upon the switching frequency fs=1/T(θ).
In the circuit of FIG. 1, however, due to propagation delays, the transistor M does not turn off immediately when the sensing voltage Vcs(t,θ) reaches the reference voltage VcsREF(θ), i.e., when the current Ip(t,θ) in the primary winding Lp reaches the provided threshold VcsREF(θ)/Rs, but remains turned on for a further time, referred to as “total propagation delay TD”, as represented in FIG. 4. In particular, the total propagation delay TD is given by the sum of the switching delay of the comparator 26, the propagation delay of the driver 30, and the turning-off delay characteristic of the power switch M. It follows that the peak current in the primary winding Lp is higher, as compared to the ideal value, by a quantity ΔIP(θ) equal to:
                              Δ          ⁢                                          ⁢                                    I              P                        ⁡                          (              θ              )                                      =                                                            Vin                ⁡                                  (                  θ                  )                                            ⁢                              T                D                                                    L              P                                .                                    (        4        )            and thus the regulated d.c. output current Iout increases with the effective value of the input voltage Vin.
To compensate for the increase in the peak current linked to the input voltage Vin, in power supplies available on the market, a positive offset voltage proportional to the input voltage Vin is added to the sensing voltage Vcs(t,θ), as illustrated in FIG. 5.
FIG. 5 shows a flyback power supply 50 similar to the power supply 1 of FIG. 1. Consequently, the elements of the flyback power supply 50 that are in common with those of the diagram of FIG. 1 are designated by the same reference numbers and the description thereof will not be repeated.
The flyback power supply 50 comprises a feed-forward resistor 51, having a resistance RFF and connected between the source terminal of the switch M and the third input terminal CS of the control module 15; and a feed-forward current source 52, generating the feed-forward current IFF and governed by a control current IZCD, which is generated by the ZCD circuit 36 and is proportional to the auxiliary current Iaux flowing in the auxiliary sensing resistor 21 during the time period when the switch M is on. For example, the control current IZCD is equal to the auxiliary current Iaux and is generated via a current mirror circuit.
On this hypothesis, since, as has been mentioned, during the on period TON of the transistor M, the second input terminal ZCD of the control module 15 is connected to the first ground 12, the auxiliary current Iaux and the control current IZCD flowing in the auxiliary sensing resistor 21 are:
                                          I            aux                    ⁡                      (            θ            )                          =                                            I              ZCD                        ⁡                          (              θ              )                                =                                    m              ⁢                                                          ⁢                              Vin                ⁡                                  (                  θ                  )                                                                    R              aux                                                          (        5        )            where m is the turn ratio between the auxiliary winding Laux and the primary winding Lp.
The feed-forward current source IFF is a current mirror that generates a current proportional to the current IZCD according to the relation:IFF(θ)=KFFIZCD(θ)where KFF is the gain of the current mirror.
The feed-forward current IFF is supplied to the feed-forward resistor 51, which generates an additional feedback voltage VFF. Setting RFF>>RS, we have:
                                          V            FF                    ⁡                      (            θ            )                          =                              K            FF                    ⁢          m          ⁢                                          ⁢                                    R              FF                                      R              aux                                ⁢                                    Vin              ⁡                              (                θ                )                                      .                                              (        6        )            
Imposing that the additional feedback voltage VFF is equal to the voltage step due to the propagation delays:ΔVCS(θ)=RSΔIP(θ)=VFF(θ)and combining with Eq. (4), we obtain the resistance value RFF of the feed-forward resistor useful for obtaining a compensation:
                              R          FF                =                              1                          K              FF                                ⁢                      1            m                    ⁢                                                    R                aux                            ⁢                              R                                  S                  ⁢                                                                                                                            L              P                                ⁢                                    T              D                        .                                              (        7        )            
In practice, the voltage supplied to the comparator 26 is increased, with respect to the voltage Vp on the primary sensing resistor 19, by a value such as to anticipate switching of the comparator 26 by a time equal to the total propagation delay TD. In this way, when the comparator 26 switches, the current IP flowing in the primary sensing resistor 19 is lower than the threshold value, and when the power switch M turns off with a delay TD, the current IP has reached the desired threshold value, as illustrated in FIG. 6.
It follows that the variation of the output current supplied by the secondary winding Ls proportional to the input voltage Vin due to the total propagation delay may be compensated thereby if the total propagation delay TD is constant. However, if the total propagation delay TD varies, also this compensation is not sufficient.
This is a problem in solid-state lighting apparatuses, where it is increasingly important to obtain a high accuracy in the d.c. output current, with values even lower than ±3%, which cannot always be achieved with the compensation technique represented in FIG. 5.
In addition, the described power supply is used with different power transistors M, according to the applications and requirements of the users. The power transistors M available on the market have similar static characteristics, in particular similar saturation resistance RDS-on, but different switching characteristics, in particular a different switching time. It follows that the output current varies according to the power transistor being used. This requires a modification and an adaptation of the value of the feed-forward resistor 51, on the basis of Eq. (7), according to the applications and to the power switch used. This setting is, however, complex and costly.